In CMOS ICs, like kinds of devices within a given well must be isolated in the same manner as the devices in either a NMOS or PMOS circuit. However, the isolation requirements of CMOS technology extend beyond those of either PMOS or NMOS alone, in that in CMOS it is also necessary to isolate the p- and n- channel devices from one another. The isolation of p-channel from n-channel devices must satisfy two requirements. The first is that any possible leakage currents that could flow between adjacent PMOS and NMOS must be suppressed. The second is that the susceptibility of CMOS to latchup must be minimized.
In CMOS structures, the isolation spacing between the n- and p-channel device is defined as the total of the distances between the edge of the n.sup.+ region of the n-channel and the edge of the p.sup.- region of the p-channel (or, in other words, the n.sup.+ to p.sup.+ spacing).
In fabricating CMOS circuits, the isolation of PMOS and NMOS is usually performed by a trench. Deep-trench processes offer the benefit of producing a latchup immune CMOS circuit. However, deep-trench structures generally require significantly increased manufacturing process complexity, and consequently result in potentially lower productivity (i.e., lower throughput and yield). To get rid of the disadvantage of deep-trench processes, shallow-trench processes are used to perform the isolation process in CMOS processes.
Shallow-trench isolation is carried out by the configuration shown in FIG. 1A. In a CMOS circuit, the NMOS 150 is established in a p-well and the PMOS 151 is established in an n-well, respectively. The p-well of NMOS 150 is used to isolate the NMOS 150 from the PMOS 151. Also, the trench 100 is used to separate the n.sup.+ region 101 of NMOS 150 and p.sup.+ region 102 of PMOS 151. To proceed with the shallow-trench isolation, it is important to form the edge 103 of p-well in a proper position. Because the p-well is used to isolate the PMOS 150 and NMOS 151, the distance between the sidewall of the p-well 103 and the p.sup.+ region 102 must be large enough to prevent the latchup of the CMOS.
To reduce the dimension of the CMOS circuit, the dimension of trench 100 must be shrunk. As the width of the trench 100 reduced, the fabrication of the p-well becomes more difficult. Because the width of the trench 100 is reduced, the alignment of the p-well mask is more difficult.
As an example of an improperly aligned p-well, FIG. 1B shows that the edge 104 of the p-well is shifted to the right and near the p.sup.+ region 102 of PMOS 151. Under these conditions, latchup easily occurs.